FNO-Based Inverse Co-Design of Semiconducting Quantum-Dot Devices

Introduction

Semiconductor quantum dots are a leading platform for spin‑based quantum processors, but their performance hinges on a delicate interplay of lithographic gate geometry and applied voltages. Traditionally, engineers iterate through cycles of fabrication and measurement, gradually refining layouts that happen to work. This empirical approach leaves much of the design space unexplored and can be prohibitively slow when targeting specific qubit characteristics such as confinement shape, tunnel coupling, or charge stability.

A recent study demonstrates how a Fourier Neural Operator (FNO) can serve as a fast, differentiable surrogate for the physics‑based Thomas–Fermi electrostatic simulator that underpins quantum‑dot design. By embedding the FNO within a gradient‑based inverse co‑design loop, researchers simultaneously optimise gate electrode patterns and bias voltages to achieve prescribed charge‑density distributions. The result is a workflow that can generate device geometries with millisecond‑scale evaluation times—orders of magnitude faster than conventional CPU simulations—while preserving sub‑percent accuracy.

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How the Inverse Co‑Design Framework Works

1. Reference Simulations – A semiclassical Thomas–Fermi model computes the two‑dimensional electron density for a variety of gate layouts and voltage settings. These data form the training set for the neural operator.

1. Training the FNO – The Fourier Neural Operator learns a mapping from the spatially varying gate potentials to the resulting charge‑density field. In testing, the surrogate reproduces densities with a relative \(L^2\) error of roughly 0.6 %, matching the fidelity of the full physics solver.

1. Defining the Target – Designers specify a desired charge‑density pattern that corresponds to a particular quantum‑dot geometry (e.g., a vertically elongated double dot). This target encodes the qubit‑relevant properties they wish to achieve.

1. Gradient‑Based Optimization – Because the FNO is differentiable, automatic‑gradient tools can compute sensitivities of the output density with respect to both gate shapes and voltages. An optimizer then adjusts these parameters, respecting fabrication constraints such as minimum feature size and alignment tolerances.

1. Batched Inference and Speed‑up – Running the FNO on a GPU yields a ~17,000‑fold speed‑up per design compared with the CPU‑based simulator. Batched inference further accelerates exploration of large parameter families, enabling rapid prototyping of multiple device concepts.

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Demonstrated Design Capabilities

Using the framework, the authors produced two distinct double‑dot configurations from identical starting conditions:

• Vertically elongated dots – Achieved by shaping the gate electrodes to confine charge along the growth direction, which can enhance spin‑orbit coupling and facilitate certain readout schemes.
• Horizontally elongated dots – Realised by stretching the confinement laterally, potentially improving tunnel coupling to neighbouring dots and enabling faster two‑qubit gates.

Both outcomes satisfy the imposed fabrication constraints, illustrating that the method can navigate trade‑offs between physical performance and manufacturability. Moreover, the ability to prescribe the spatial charge profile directly translates into control over key qubit metrics such as valley splitting, exchange interaction strength, and susceptibility to charge noise.

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Practical Implications for Quantum‑Hardware Development

The integration of an FNO surrogate into the design loop offers several tangible benefits for research labs and industry teams:

• Accelerated Design Cycles – Millisecond‑scale evaluations allow engineers to iterate through thousands of candidate layouts in the time it previously took to run a single high‑fidelity simulation.
• Exploration of Novel Geometries – By removing the computational bottleneck, designers can venture beyond conventional gate patterns, potentially discovering architectures that improve coherence or scalability.
• Pre‑Fabrication Validation – Targeted charge‑density maps serve as a predictive checkpoint, reducing the risk of costly fabrication failures.
• Scalable Co‑Design – The same framework can be extended to multi‑dot arrays, enabling systematic optimisation of larger quantum‑processor modules.

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Closing Thoughts

Fourier Neural Operators provide a compelling bridge between accurate electrostatic modelling and the speed required for modern optimisation workflows. By coupling this surrogate with gradient‑based inverse design, the study showcases a practical pathway to engineer semiconductor quantum‑dot devices with bespoke confinement characteristics before any wafer is processed. As quantum hardware moves toward larger, more complex qubit arrays, such data‑driven co‑design tools will become essential for meeting the stringent performance targets of fault‑tolerant quantum computing.