Parallel quantum gates now possible on larger qubit arrays

Introduction

A recent breakthrough from Shenzhen University and the Quantum Science Center demonstrates that parallel quantum gates can be executed on large qubit arrays—up to 200 superconducting qubits—while keeping error growth linear rather than exponential. By treating the processor as a collection of small, constant‑sized subsystems and designing control pulses that are robust to inter‑subsystem crosstalk, the team achieved order‑of‑magnitude fidelity gains for both single‑ and multi‑qubit operations. The approach works across diverse platforms, including nitrogen‑vacancy (NV) centers and nuclear‑spin processors, offering a versatile path toward scalable quantum computers.

Subsystem‑Based Crosstalk Suppression

Traditional gate design optimizes control pulses for the entire processor, a task that quickly becomes intractable as the number of qubits grows. The new method partitions the full system \(S\) into disjoint subsystems \(S1\cup\dots\cup SL\), each containing only a few qubits. By assuming that crosstalk between subsystems is weak, the optimization problem collapses to a set of independent, low‑dimensional control tasks. This "crosstalk‑robust control over constant‑sized subsystems" eliminates the leading‑order error terms that normally dominate parallel gate performance.

Key points of the subsystem framework:

• Dynamic partitioning – the division into subsystems can change for different gates, matching the logical structure of the circuit.
• No prior crosstalk knowledge – the pulse design does not require precise values of coupling strengths, making it hardware‑agnostic.
• Reduced computational load – only a handful of directional derivatives are needed per subsystem, cutting optimization time dramatically.

Linear Noise Scaling for Parallel Single‑Qubit Gates

Numerical simulations show that robust pulses maintain a linear decay of fidelity with the number of repeated parallel gates, in stark contrast to the exponential decay observed with primitive rectangular pulses. Mathematically, the infidelity \(\epsilon\) scales as \(1-\epsilon M\) rather than \(e^{-\epsilon M}\) for \(M\) repeated gates. This shift means that even when many gates are applied simultaneously, the accumulated error grows predictably and remains manageable, a crucial requirement for deep quantum circuits.

Order‑of‑Magnitude Gains for Multi‑Qubit Operations

For parallel two‑qubit gates such as CZ or CNOT, the subsystem approach yields an order‑of‑magnitude reduction in error rates. Simulations across three hardware families—superconducting qubits, coupled NV centers, and a 12‑qubit nuclear‑spin processor—demonstrated consistent improvements. In particular, the robust pulse design reduced the decay rate of parallel CNOT fidelity by roughly a factor of 13 compared with primitive pulses.

Practical Implications and Future Directions

The ability to run high‑fidelity parallel gates on hundreds of qubits opens several immediate opportunities:

1. Deeper quantum algorithms – Linear noise scaling permits longer circuit depths without prohibitive error accumulation.
2. Scalable quantum simulation – Larger, more coherent arrays can tackle classically intractable many‑body problems.
3. Hardware‑agnostic control – Since the method does not rely on detailed crosstalk parameters, it can be deployed on emerging architectures with minimal re‑engineering.

Looking ahead, integrating this subsystem‑based control with error‑correction protocols could further suppress logical error rates, bringing fault‑tolerant quantum computing closer to reality. Continued experimental validation on full‑scale processors will be essential to confirm the predicted scaling in real devices.

--- Bottom line: By reframing parallel gate design as a robust, subsystem‑level optimization problem, researchers have turned exponential error growth into a linear trend, enabling reliable parallel operations on qubit arrays far larger than previously possible. This advance paves the way for more powerful quantum processors across a variety of hardware platforms.